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RM0008
14.4.18
General-purpose timer (TIMx)
TIMx DMA address for full transfer (TIMx_DMAR)
Address offset: 0x4C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMAB[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 DMAB[15:0] : DMA register for burst accesses
A read or write access to the DMAR register accesses the register located at the address:
“(TIMx_CR1 address) + DBA + (DMA index)” in which:
TIMx_CR1 address is the address of the control register 1,
DBA is the DMA base address configured in the TIMx_DCR register,
DMA index is the offset automatically controlled by the DMA transfer, depending on the
length of the transfer DBL in the TIMx_DCR register.
14.4.19
Table 78.
TIMx register map
TIMx registers are mapped as 16-bit addressable registers as described in the table below:
TIMx register map and reset values
Offset
Register
0x00
TIMx_CR1
Reserved
CKD
[1:0]
CMS
[1:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0x04
TIMx_CR2
Reserved
MMS[2:0]
Reserved
Reset value
0
0
0
0
0
0x08
TIMx_SMCR
Reserved
ETPS
[1:0]
ETF[3:0]
TS[2:0]
SMS[2:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0C
TIMx_DIER
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0x10
TIMx_SR
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0x14
TIMx_EGR
Reserved
Reset value
0
0
0
0
0
0
TIMx_CCMR1
Output Compare
mode
Reserved
OC2M
[2:0]
CC2S
[1:0]
OC1M
[2:0]
CC1S
[1:0]
0x18
Reset value
TIMx_CCMR1
Input Capture
mode
Reset value
Reserved
0
0
0 0
IC2F[3:0]
0
0
0
0
0 0 0 0 0 0 0 0
IC2
CC2S
PSC IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0
Doc ID 13902 Rev 9
373/995
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